1. Field of the Invention
The present invention relates to element isolation techniques, and especially to element isolation regarding MIS (Metal Insulator Semiconductor) transistors formed on an SOI (Silicon On Insulator) substrate.
2. Description of the Background Art
It is known that an insulating film is used in an element isolation technique for isolating a plurality of MIS transistors (MOS transistors, for example). The insulating film for element isolation is formed by a process from the surface of a semiconductor substrate on which the MOS transistors are to be formed.
In the so-called bulk type MOS transistor, namely a MOS transistor including a source region and a drain region by forming high concentration impurity layers restrictively in the surface of a semiconductor substrate, a region left between the source and drain regions in the semiconductor substrate is connected to the surface of the semiconductor substrate as well. This allows the potential of the so-called back gate (semiconductor layer capable of forming a channel in a position facing a gate) to be controlled easily from the surface side of the semiconductor substrate.
However, a semiconductor layer in an SOI substrate is typically thin so that the source region, drain region and the insulating film for element isolation are formed reaching the so-called buried insulating layer. A technique of separating the insulating film for element isolation from the buried insulating layer has therefore been proposed in order to easily fix the potential of the so-called body region that is interposed between the source and drain regions and faces a gate electrode on the opposite side to the buried insulating layer. For example, the potential of the body region is controlled via an impurity region provided between the insulating film for element isolation and the buried insulating layer. Such technique is introduced in, for example, Japanese Patent Application Laid-Open Nos. 11-340472 (1999), 2004-193146, 2002-217420 and 2000-243973, and a publication entitled “Bulk-Layout-Compatible 0.18-μm SOI-MOS Technology Using Body-Tied Partial-Trench-Isolation (PTI)”, by Yuuichi Hirano, et al., IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 12, DECEMBER 2001.
The simple separation of the insulating film for element isolation from the buried insulating layer, however, will result in a pn junction being formed and resultant capacitance being generated between the source and drain regions and the impurity layer left between the insulating film for element isolation and the buried insulating layer. This causes an increase in parasitic capacitance of the source and drain regions.
In addition, a gate electrode and wiring connected to the source and drain regions are installed on the insulating film for element isolation as well. That causes the impurity layer left between the insulating film for element isolation and the buried insulating layer to contribute to an increase in parasitic capacitance of the wiring.